The present invention relates to a semiconductor memory device and, more particularly, to an improvement in a data output circuit of a random access memory device incorporated with a test circuit.
As well known in the art, a semiconductor memory device is required to have a memory cell correctly storing-logic "1" or "0" indicative of data and a data read/write circuit correctly operating to read and write data from and into a selected memory cell. It is therefore required to test the memory device to ensure the corrective operation of each memory cell and the date read/write circuit. In order to facilitate the test operation, a test circuit is incorporated into the memory device in general.
Referring to FIG. 1, a prior art memory device 100 includes first and second memory cell arrays 6-1 and 6-2. Each of the cell arrays 6-1 and 6-2 has such a circuit construction as shown in FIG. 2. Particularly, the memory cell array 6 includes two pairs of data input/output lines Ioi, Ioi and Ioj, Ioj, a plurality of column switches YSW, a plurality of sense amplifiers SA and a memory cell portion MC. The memory cell portion MC includes a plurality of word lines WL, a plurality pairs of bit lines DL and DL and a plurality of memory cells each disposed at a different one of intersections of the word and bit lines. Since this memory circuit is well known in the art, the further description will be omitted.
Referring back to FIG. 1, the data input/output line pairs (Io0, Io0) to (Io3, Io3) from the memory cell arrays 6 are connected to data amplifiers DA0 to DA3 respectively. The data amplifiers DA0-DA3 are in turn connected to data bus lines RWB0-RWB3, respectively. Connected between the data bus lines RWB and an output terminal DOUT is an output circuit 9. Although not shown, the memory device 100 further includes an address buffer/decoder circuit as well as a data write circuit, as well known in the art.
The memory device 100 thus constructed performs data read and write operations on one memory cell in a selected one of the arrays 6 in a normal operation. As mentioned hereinbefore, it is required to test a circuit operation. For this purpose, a test data is written into a selected memory cell and then the data stored in that memory cell is read out therefrom. At this time, if the test data write operation would be carried out one cell by one, it would take a relatively long time period. Therefore, the memory device 100 is constructed such that a plurality of memory cells are selected and written with the same data simultaneously with each other in a test operation mode. Further, there is provided one output terminal DOUT, and hence it is impossible to simultaneously read out data from the selected two or more memory cells. Accordingly, the output circuit 9 is provided with a comparator circuit to compare the data read out from the two or more selected memory cells and the comparison resultant data is outputted from the terminal DOUT. In this memory device 100, two memory cells in each of the cell arrays 6, i.e. four memory cells in total, are selected simultaneously in a test mode. Moreover, this memory device 100 further supports such another test mode that one memory cell in each of the cell array blocks 6, i.e. two memory cells in total, are selected simultaneously. In the following description, the former test mode is called a first test mode and the latter test mode is done as a second one.
When a normal mode as a read operation is designated by the high level of test signals TE1 and TE2 (FIG. 3), one of column selection signals YiTiN, YiTjN, YiNjT and YiTjT takes an active high level by an address decoder circuit ASG comprising NAND gates G14-G22 and inverters I15-I21, and the remaining column selection signals take the low level. Consequently, one of data amplifiers DA0-DA3 is activated by the corresponding high level column selection signal to respond to data appearing on the corresponding data line pair Ioi, Ioi. The activated data amplifier DA then outputs onto the corresponding data bus RWB logic "1" or "0" indicative of the data supplied thereto. In the normal data read mode, the data outputted by the activated data amplifier DA Data is transferred an input node RD via a corresponding one of inverters I0-I3 and activated or switched one of transfer-gates TG0-TG3, which is controlled by switching control signals SW0-SW3 generated by a switch signal generator SSG1 (FIG. 5) comprising NAND gates G24-G27, inverters I23-I29 and NOR gates G28 and G29. The data on the selected data bus RWBS is further transferred to an input node RD via the corresponding one of transfer-gates TG4-TG7 controlled by switching signals SW0-SW3. The input nodes RD and RD are connected to one input ends of NOR gates G8 and G9, respectively, each of which has the other input end connected in common to the output end of a NAND gate G7. This gate G7 outputs the low level at a timing of driving the data terminal DOUT. Assuming that the data outputted by the activated data amplifier DA takes the high level, the input nodes RD and RD are changed to the low and high levels, respectively, to turn a P-channel MOS transistor TO1 on and an N-channel MOS transistor TO2 off. The output terminal DOUT is thus driven to the high level.
In a normal data write mode, both of the transistors TO1 and TO2 are maintained in the nonconductive state to bring the output terminal DOUT into a high impedance. On the other hand, the data write circuit (not shown) is activated to write data into a selected one of the memory cells.
When the test signal TE1 is changed to the active low level while holding the test signal TE2 at the high level, the first test mode is designated. In this mode, four memory cells are selected as mentioned above and the test data are first stored therein. Thereafter, the device is brought into a read mode, whereby all the data amplifiers DA0-DA3 are activated because all the selection signals YiTiN, YiTjN, YiNjT and YiTjT become the high level. At this time, the transfer gates TG0-TG7 and TG10-TG13 are closed, whereas the those TG8 and TG9 are made open. Accordingly, the respective data read out from the selected memory cells and transferred onto the data bus RWB through the data amplifiers DA are supplied to a NOR gate G1 and further to a NAND gate G2 whose outputs are in turn transferred to the nodes RD and RD. When the selected four memory cell are correctly stored the test data of "1" and the data read circuit correctly reads out the same therefrom, only the transistor TO1 is turned on to drive the output terminal DOUT to the high level. In the case of the test data being "0", the transistor TO 2 is turned on to drive the terminal DOUT to the low level. If some defective portion in circuit operation exists to transfer onto at least one data bus RWB such a data as being different from the remaining data, however, the gate G1 outputs the low level, whereas the gate G2 outputs the high level. For this reason, both of the transistors TO1 and TO2 are held at the non-conductive state to bring the output terminal DOUT into a high impedance state. Thus, four test bit data are compared with one another in the device 100 and the comparison resultant data is outputted from the terminal DOUT as the logic "1" or "0" or a high impedance state.
The second test mode is designated by the low level of the test signal TE2 and the high level of the signal TE1. Two data amplifiers DA0 and DA2 or DA1 and DA3 are thereby activated by an address signal YPiT shown in FIG. 3. When a address signal YPiT ia at the high level, the data amplifiers DA0 and DA2 are activated by column address signals YiNjN and YiNjT. In the case where the address signal YPiT is at the low level, on the other hand, the data amplifiers DA1 and DA3 are activated. In the same manner as described with reference to the first test mode, two bit data read out from the selected two memory cells are compared in the output circuit 9 by use of gates G3-G6 and G8 and G9 to output the comparison resultant data.
As apparent from the above description, the access path in the test mode is different from that in the normal mode. For this reason, an access check for a read access time cannot in the test mode simultaneously with a data read/write operation test. Moreover, when a data read/write operation test other than two or four bit data is further required, other circuits therefor are needed to thereby make the total circuit configuration complicated.